Semiconductor elements operable at a high temperature (high-temperature operation compatible semiconductor elements) are, in some cases other than when packaged as stand-alone elements, put into operation as mounted on mounting boards. There are proposed many electrode structures on back faces of semiconductor elements for joining the high-temperature operable semiconductor elements and the mounting boards together, in order to make the high-temperature operable semiconductor elements and the mounting boards to be stably joined for a long period of time. Meanwhile, when semiconductor elements operable at a normal range temperature are joined to the mounting boards, in order to make a solder Pb(lead)-free or to realize a low-temperature joining, they are in some cases joined by using an Sn (tin)-base solder, a metal-nanoparticles paste and the like. Also for the high-temperature operable semiconductor elements, there are proposed many electrode structures on the back faces of the semiconductor elements for joining the high-temperature operable semiconductor elements and the mounting boards by using an Sn-base solder, a metal-nanoparticles paste and the like.
An Sn-base solder is mainly used for low-temperature joining of a semiconductor element, and is promising as a Pb-free solder. A metal-nanoparticles paste contains metal nanoparticles as main components, and can be lowered in its melting point or sintering temperature to several hundreds degree C. or less.
In Patent Document 1, a structure of a back face electrode of semiconductor element is described, in which a Ni (nickel) silicide layer, a Ti (titanium) layer (first metal layer), a Ni (nickel)) layer (second metal layer) and an Au (gold) layer (third metal layer) are sequentially stacked on a semiconductor substrate consisting mainly of Si(silicon). Patent Document 1 is a document related to a semiconductor substrate for preventing a nickel silicide layer (ohmic electrode) on a back face of a semiconductor element from peeling off, and a method for manufacturing the semiconductor substrate. The structure of the back face electrode in Patent Document 1 is characterized in that, it is achieved by lowering a temperature for forming the Ni silicide layer to from 100 to 300° C. after sequentially stacked a first Ni layer, the Ti layer, the second Ni layer and the Au layer on the semiconductor substrate consisting mainly of silicon, so that a Ni layer portion remains in the Ni silicide layer at a side thereof opposite to the side toward the substrate, and a stress applicable to the stacked metal layers on the remaining Ni layer is reduced, to thereby enhance its adhesion to the substrate.